The invention relates to a process for planarization of substrates in semiconductor engineering by removal of a layer which can consist of metal, for example copper or aluminum, or of another substance such as polycrystalline silicon, polycrystalline suicides or silicon dioxide (SiO2), from the semiconductor substrates.
In particular the process as claimed in the invention relates to removing this coating by planarization such that the layer on the surface of the semiconductor substrate is removed, but remains in trenches or contact holes which are provided in the semiconductor substrate so that conductor tracks or insulating tracks form there.
It will be possible to carry out the process as claimed in the invention without a prior (mechanical) polishing step in one step using a liquid etching medium.
U.S. Pat. No. 5,486,234 A discloses a process for removing metal which is located on the one hand on the surface of a substrate and on the other in trenches or contact holes in the substrate.
FIGS. 1a through 1d show the process known from U.S. Pat. No. 5,486,234 A using a schematic section through a semiconductor substrate. FIG. 1a shows semiconductor substrate 1 on which insulator layer 2 (for example, a layer of silicon dioxide (SiO2) is applied, into which by means of lithography trenches have been etched which are later to represent conductor tracks. A thin barrier layer which is not shown, for example, of titanium, is applied to this insulator layer 2. Then metal layer 3 is applied to this barrier layer. Application of metal layer 3 (see FIG. 1b) can take place by electroplating. Surface 4 of metal layer 3 shows trenches 5 which are known, although they are not shown in FIG. 3 of U.S. Pat. No. 5,486,234 A. If uniformly acting etching is used, these trenches would become deeper, so that it is not possible to achieve the desired end result (FIG. 1d) by subjecting the substrate shown in FIG. 1b to a uniform etching process. The previously known metal etching processes (spraying, dripping of etching media onto the surface of a rotating semiconductor substrate (wafer) makes an intermediate step necessary in order to remove most of the metal of metal layer 3 which was applied to the barrier layer. This is done to ensure that before etching begins surface 6 is flat, as shown in FIG. 1c. This polishing (levelling off) can be electropolishing, as suggested in U.S. Pat. No. 5,486,234.
Another disadvantage of the known spray and drip etching is that only low etching rates (0.02 to 1.34 μ/min) are reached. In order to achieve the desired result within a reasonable period of time, most of the metal of layer 3 must be removed using another process (for example, by electropolishing).
EP 0 223 920 B1 describes plasma etching or reactive ion etching with planarization means (for example SOG=spin on glass) as a planarization method. In particular, EP 0 223 920 B1 suggests the known process of chemical mechanical polishing as the planarization process.